The present invention relates to integrated memory devices and more particularly to data transfer in memory devices.
Within a high-speed memory system 38, shown in FIG. 1, a synchronous memory device 40 performs operations, such as reading from or writing to a memory array 46, in a predetermined sequence. These operations are generally performed responsive to commands COM issued by a command generator, such as a memory controller 44. Timing of the commands and other signals outside of the memory device 40 is determined by an external clock signal CKEXT and a data clock DCLK that are produced by the memory controller 44.
It will be understood by one skilled in the art that the block diagram of FIG. 1 omits some signals applied to the memory device 40 for purposes of brevity. Also, one skilled in the art will understand that although in the exemplary embodiment disclosed herein, the commands COM are control data within a control data packet, in other applications the commands may be composed of a combination of command signals. In either case, the control data or combination of signals is commonly referred to as a command. The exact nature of these packets or signals will depend on the nature of the memory device 40, but the principles explained herein are applicable to many types of memory devices, including packetized DRAMs and other synchronous DRAMs.
Within the memory device 40, operations are controlled by a logic control circuit 42 responsive to the commands COM. In the packetized memory system 38 of FIG. 1, the logic control circuit 42 includes a command sequencer and decoder 45 and command latches 50. In a conventional memory system, the logic control circuit 42 may be conventional DRAM control logic.
Timing of operations within the memory device 40 is controlled by an internal clock signal CKINT that is produced by a delay-locked loop 62 and a switching circuit 63 responsive to the external clock signal CKEXT. Timing of data being latched into the memory device 40 is controlled by a write latch signal LATCHW produced by a pulse generator 61 responsive to the data clock DCLK. Data is transferred out of the memory device 40 through an output circuit 81 responsive to an internal read latch signal LATCHR.
Usually, operations within the memory device 40 must be synchronized to operations outside of the memory device 40. For example, commands and data are transferred into the memory device 40 on command and data busses 48, 49, respectively, by clocking a command latch/buffer 50 and input data latches 52 according to the internal clock signal CKINT and the internal write latch signal LATCHW. However, as noted above, command timing on the command bus 48 and data timing on the data bus 49 are controlled by the external clock signal CKEXT and the data clock DCLK, respectively. Therefore, to transfer commands and data from the busses 48, 49 at the proper times relative to the external clock signal CKEXT, the internal clock signal CKINT is synchronized to the external clock signal CKEXT and the write latch signal LATCHW is synchronized to the data clock DCLK.
To establish synchronization of the internal and external timing, the memory device 40 produces several phase-shifted clock signals CKINTxe2x88x92xcfx86x at respective taps of the delay-locked loop 62 responsive to the external clock signal CKEXT. Each of the phase-shifted clock signals CKINTxe2x88x92xcfx86x has a respective phase-shift xcfx86x relative to the external clock signal CKEXT. In response to commands COM from the memory controller 44, the logic control circuit 42 activates the switching circuit 63 to select one of the phase-shifted clock signals CKINTxe2x88x92xcfx861 as the internal clock signal CKINT. The selected phase-shifted clock signal CKINTxe2x88x92xcfx861 has a phase-shiftxcfx861corresponding to delays within the memory device 40 and propagation delays of the external clock signal CKEXT. Because the shifted internal clock signal CKINTxe2x88x92xcfx861 is synchronized to the external clock signal CKEXT, operations within the memory device 40 can be synchronized to commands and data arriving on the command bus 48 and data bus 49.
The command packet contains control and address information for each memory transfer, and a command flag signal CDFLAG identifies the start of a command packet which may include more than one 10-bit packet word. In fact, a command packet is generally in the form of a sequence of 10-bit packet words on the 10-bit command bus 48. The command latch/buffer 50 receives the command packet from the bus 48, and compares at least a portion of the command packet to identifying data from an ID register 47 to determine if the command packet is directed to the memory device 40 or some other memory device. If the command buffer determines that the command packet is directed to the memory device 40, it then provides a command word to the command decoder and sequencer 45. The command decoder and sequencer 45 generates a large number of internal control signals to control the operation of the memory device 40 during a memory transfer.
An address capture/sequencer/refresh circuit 51 also receives the command words from the command bus 48 and produces a 3-bit bank address, a 10-bit row address, and a 7-bit column address corresponding to address information in the command or to addresses from a refresh counter (not shown).
One of the problems of conventional DRAMs is their relatively low speed resulting from the time required to precharge and equilibrate circuitry in the DRAM array. The packetized DRAM 40 shown in FIG. 2 largely avoids this problem by using a plurality of memory banks 46, in this case eight memory banks 46a-h. After a memory is read from one bank 46, the bank 46 can be precharged while the remaining banks 46b-h are being accessed. Each of the memory banks 46a-h receive a row address from a respective row latch/decoder/driver 59a-h. All of the row latch/decoder/drivers 59a-h receive the same row address from the address capture/sequencer/refresh circuit 51. However, only one of the row latch/decoder/drivers 46a-h is active at any one time as determined by bank control logic 65 as a function of bank data from the address capture/sequencer/refresh circuit 51.
The 7-bit column address is applied to a column latch/decoder 66 which supplies I/O gating signals to an I/O interface 54. The I/O interface 54 interfaces with columns of the memory banks 46a-h through sense amplifiers 75.
To write data to the memory device 40, data are received at a latching circuit 52 responsive to the write latch signal LATCHW. The data are then transferred to a write latch/register 53 where the data are made available to the I/O interface 54. The sense amplifiers 75 can then provide the data to the appropriate location indicated by the row, bank, and column addresses.
For reading data from the memory device 40, the I/O interface 54, shown in FIGS. 1 and 2, under control of the logic control circuit 42 prefetches 64 bits of data from a memory array 46 and transfers the prefetched data to the output circuit 81 responsive to the internal clock signal CKINT. The I/O interface 54 includes a set of sense amplifiers 75 for each complementary digit line pair. For example, an array having 512 digit line pairs would include 512 sense amplifiers 75 that read data from the digit lines and provide complementary output data in response. A set of multiplexers 91 receive the complementary data from the sense amplifiers 75 and, responsive to a control signal from the logic control circuit 42, output the 64 bits of complementary data. As shown in FIG. 2 for the example described above of a 512 column array, the multiplexers 91 would be 8-to-1 multiplexers so that each multiplexer 91 would output data from one of 8 digit line pairs.
The output data from each multiplexer 91 in the multiplexer bank are then applied to a line driver 77 which is typically formed from a DC sense amplifier or a helper flipflop. The line driver converts the low drive current signals from the sense amplifiers 75 and multiplexer 91 to corresponding signals with higher current capability. The line drivers 77 output the complementary data on a corresponding complementary pair of lines 85 that carry the data from the line drivers 77 to the output circuit 81 where the data are received by a second bank of multiplexers 93. The second bank of multiplexers 93 multiplexes the 64 bits by a factor of four to provide four sets of 16 bits that are input to a series of four pairs of 16-bit output registers 79. Since there are complementary data signals for each bit, each bit utilizes two registers (a bit register and a complementary bit register). As best seen in FIG. 2, for each complementary line pair, the output circuit 81 includes eight output registers that receive the data responsive to the internal clock signal CKINT. The data in the eight output registers are latched into a tri-state output buffer 83 by the read latch signal LATCHR and each tri-state output buffer 83 outputs four bits of output data to respective lines of the 16 line data bus 49. The read latch signal LATCHR has a frequency twice that of the internal clock signal CKINT because the pulses of the read latch signal LATCHR are produced by the output vernier 57 responsive to both rising and falling edges of the internal clock signal CKINT. Thus, the data are transferred from the eight output registers 79 to the data bus 49 over a period about equal to two cycles of the internal clock signal CKINT.
During testing of the memory device, data are written to the memory array 46 in a selected test pattern. Data are then read from the memory array 46 and compared to the selected test pattern. If data read from a location in the array 46 does not match the data written to the location, the tri-state buffer 83 is driven to a tri-state condition. In the tri-state condition, the buffer 83 presents a high impedance, floating output to the data bus 49. A test head 110 indicates the tri-state condition to test circuitry 112 that identify the erroneous data. A redundant row or column can then replace the row or column having the defective location.
Because the memory device 40 is operated and tested at high speeds, the time during which the tri-state condition is present on the data bus 49 can be very short. At very high frequencies, capacitance and inductance of the data bus 49 and the test head 110 can make the tri-state condition very difficult to detect.
Another problem arises from the number of lines carrying data. Because each bit of data occupies two conductors, the device described above employing 64 data bits and a 16-bit data bus utilizes 128 lines to transfer 64 data bits from the line drivers 77 to the output latch circuit 81. Each of these lines occupies valuable space on the substrate containing the memory array 46 and complicates routing of lines.
An I/O circuit in a memory device reads data from a memory array and a comparing circuit compares the data to a desired pattern. If the read data is incorrect, the comparing circuit outputs a flag signal to a tri-state output buffer. The tri-state output buffer produces an error indicator in response. In one embodiment, the error indicator is a high-impedance floating signal that is detected by a test system. The flag signal disables the output buffer for a plurality of clock transitions so that the tri-state indicator is present for a sufficiently long period for the test system to detect the tri-state indicator.
In one embodiment, data from the memory array is read by sense amplifiers that produce complementary data in response. The complementary data are compressed by multiplexers in response to selected bits of an address signal to produce 64 bits of complementary data. The 64 bits of complementary data are applied to line drivers formed from DC sense amplifiers and helper flip-flops. In response to the complementary data, the DC sense amplifiers and helper flip-flops output single-ended data.
Because the flag signal corresponds to a plurality of data bits, the plurality of data bits and the error signal can be transmitted on fewer conductors rather than requiring a pair of conductors for each data bit, therefore reducing the number of conductors between the I/O circuit and the tri-state buffer. Also, because the error signal corresponding to a plurality of data bits can be stored in a single register, the number of output registers is reduced.